Work

Use of increased transistor gate length for leakage reduction in caches

Year: 2010

Type: conference-paper

Source: IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

DOI: 10.1109/mwscas.2010.5548675

Authors: Savithra Eratne, Claudia Romo, Eugene John

Institution: The University of Texas at San Antonio

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2019274652

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Cites: 9

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Related to: 10