Work

A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead

Year: 2010

Type: conference-paper

Source: International Symposium on Quality Electronic Design (ISQED)

DOI: 10.1109/isqed.2010.5450397

Authors: Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dhiraj K. Pradhan

Institutions: University of Bristol, Government of India, Department of Telecommunications, University of North Texas

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2020223369

FWCI: 3.85

Cites: 17

Cited by: 14

Related to: 10