Work

A multiple delay simulator for MOS LSI circuits

Year: 1980

Type: conference-paper

Abstract: This paper describes a multiple delay simulator for MOS LSI circuits. The basic primitives for this simulator are MOS transistor structures where the transistors are evaluated logically. Integer rise and fall delays are associated with each transition and these delays are computed automatically based on device characteristics and circuit capacitances. The simulator has been extensively used for the design verification of production LSI chips.

Source: ACM/IEEE Design Automation Conference (DAC)

DOI: 10.1145/800139.804594

Authors: H. N. Nham, A. K. Bose

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: bronze

OpenAlex ID: W2034468751

FWCI: 12.59

Cites: 10

Cited by: 49

Related to: 10