Work

Stress-enhancement technique in narrowing NMOSFETs with damascene-gate process and tensile liner

Year: 2009

Type: conference-paper

Source: International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

DOI: 10.1109/vtsa.2009.5159273

Authors: S. Mayuzumi, S. Yamakawa, Y. Tateshita, M. Tsukamoto, H. Wakabayashi, T. Ohno, N. Nagashima

Institution: Sony (Japan)

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2071660003

FWCI: 0.469

Cites: 1

Cited by: 2

Related to: 10