Achieveing reduced area by Multi-bit Flip flop design
Year: 2013
Type: conference-paper
Authors: G. Prakash, K. Sathishkumar, B. Sakthibharathi, S. Saravanan, R. Vijaysai
Institution: SASTRA University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W2090628554
