Work

FPGA implementation using Renoir tools: application for bit timing logic (BTL) synthesis of controller area network with 100% free error

Year: 2002

Type: conference-paper

DOI: 10.1109/icm.1998.825560

Authors: K. Abouda, J. Ducaud, H. Henry, J.L. Aucouturier

Institutions: Centre National de la Recherche Scientifique, Université Bordeaux-I

Language: English

Topic: Embedded Systems and FPGA Applications

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2104696146

FWCI: 0.375

Cites:

Cited by: 1

Related to: 10