Work

An FFT Core for DVB‐T/DVB‐H Receivers

Year: 2008

Type: article

Abstract: This paper presents the design and implementation of a 2K/4K/8K multiple mode FFT core for DVB‐T/DVB‐H receivers. The proposed core is based on a pipeline radix‐22 SDF architecture. The necessary changes in the radix‐22 SDF architecture to achieve an efficient FFT implementation are detailed. Quantization effects and timing design parameters are analyzed for DVB‐T/DVB‐H. Area and power results are provided for the proposed core.

Source: VLSI design

DOI: 10.1155/2008/610420

Authors: A. Cortés, I. Vélez, I. Zalbide, A. Irizar, J. F. Sevillano

Institutions: Centro de Estudios e Investigaciones Técnicas de Gipuzkoa, Universidad de Navarra

Language: English

Topic: Digital Filter Design and Implementation

Subfield: Signal Processing

Field: Computer Science

Domain: Physical Sciences

Open Access status: hybrid

Funders: Eusko Jaurlaritza, European Regional Development Fund, European Social Fund