Hysteresis cycle in the latch-up characteristic of wide CMOS structures
Year: 1988
Type: article
Abstract: Experimental results are interpreted in terms of a simple lumped-element model that is also used to reproduce the hysteresis phenomenon with discrete components. The hysteresis is related to a three-dimensional (3-D) nonuniformity in the current distribution. Such hysteresis can lead to an erroneous evaluation of latchup parameters, such as the holding current density.>
Source: IEEE Electron Device Letters
DOI: 10.1109/55.694
Authors: L. Selmi, E. Sangiorgi, G. Crisenza, D. Re, B. Ricco
Institutions: University of Bologna, University of Udine
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W2108297137