Work

Gate capacitances behavior of nanometer FD SOI CMOS devices with HfO/sub 2/ high-k gate dielectric considering vertical and fringing displacement effects using 2-D Simulation

Year: 2006

Type: article

Source: IEEE Transactions on Electron Devices

DOI: 10.1109/ted.2006.874157

Authors: Yu-Sheng Lin, Chia-Hong Lin, J.B. Kuo, Ke-Wei Su

Institutions: National Taiwan University, Taiwan Semiconductor Manufacturing Company (Taiwan)

Language: English

Topic: Semiconductor materials and devices

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funder: National Taiwan University

OpenAlex ID: W2136456367

FWCI: 0.647

Cites: 15

Cited by: 6

Related to: 10