Work

Phase noise in frequency divider circuits

Year: 2008

Type: conference-paper

Abstract: We identify limitations of the models for phase noise in frequency dividers by Egan and by Phillips and present a new model applicable to both high frequency and low power frequency divider design. Further, we design both synchronous and asynchronous frequency divider test chips that allow us to observe experimentally the effects of noise accumulation, sampling frequency and biasing conditions on the total phase noise performance of frequency dividers. We use our measurements to validate the simulated values obtained by time domain phase noise analysis offered by the commercial simulator Spectre RF. The measured data show good agreement with the simulation results.

Source: IEEE International Symposium on Circuits and Systems proceedings

DOI: 10.1109/iscas.2008.4541973

Authors: Melina Apostolidou, Peter G.M. Baltus, Cicero S. Vaucher

Institutions: NXP (Netherlands), Eindhoven University of Technology

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W2138498299

FWCI: 0.948

Cites: 5

Cited by: 12

Related to: 10