Modelling hardware verification concerns specified in the e language: an experience report
Year: 2009
Type: conference-paper
Abstract: e is an aspect-oriented hardware verification language that is widely used to verify the design of electronic circuits through the development and execution of testbenches. In recent years, the continued growth of the testbenches developed at Infineon Technologies has resulted in their becoming difficult to understand, maintain and extend. Consequently, a decision was taken to document the testbenches at a higher level of abstraction. Accordingly, we attempted to model our legacy test suites with an existing aspect-oriented modelling approach. In this paper we describe our experience of applying Theme/UML, an aspect-oriented modelling approach, to the representation of aspect-oriented testbenches implemented in e. It emerged that the common aspect-oriented concepts supported by Theme/UML were not sufficient to adequately represent the e language, primarily due to e's dynamic, temporal nature. Based on this experience we propose a number of requirements that must be addressed before aspect-oriented modelling approaches such as Theme/UML are capable of representing aspect-oriented systems implemented in e.
Authors: Darren Galpin, Cormac Driver, Siobhán Clarke
Language: English
Subfield: Software
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
Funder: Science Foundation Ireland
OpenAlex ID: W2138752159