Work

A parallel flop synchronizer for bridging asynchronous clock domains

Year: 2004

Type: conference-paper

Source: AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

DOI: 10.1109/apasic.2004.1349443

Authors: Suk-Jin Kim, Jeong-Gun Lee, Kiseon Kim

Institution: Gwangju Institute of Science and Technology

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2139356211

FWCI: 0.83

Cites: 7

Cited by: 8

Related to: 10