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Quick and Clean: Stencil Lithography for Wafer-Scale Fabrication of Superconducting Tunnel Junctions

Year: 2009

Type: article

Abstract: This paper presents a resist-less process for parallel fabrication of sub-micrometer Al-AlOx-Al superconducting tunnel junctions. A custom stencil is fabricated containing 200 nm low-stress SiN membranes with micro-apertures. The stencil is aligned and clamped with a 1 mum accuracy to a substrate wafer containing Ti-Au contact electrodes. The junctions are fabricated by evaporating Al from two different angles, with an intermediate in-situ oxidation step. Measurements of the devices down to 0.3 K show stencil lithography is a good candidate for parallel, resist-less patterning of sub-micrometer area tunnel junctions. Challenges are addressed and further developments are proposed.

Source: IEEE Transactions on Applied Superconductivity

DOI: 10.1109/tasc.2009.2019075

Authors: V. Savu, J. Kivioja, J. Ahopelto, J. Brugger

Institutions: École Polytechnique Fédérale de Lausanne, VTT Technical Research Centre of Finland

Language: English

Topic: Superconducting and THz Device Technology

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: green

OpenAlex ID: W2139463373

FWCI: 1.011

Cites: 10

Cited by: 11

Related to: 10