A 0.18 /spl mu/m CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications
Year: 1999
Type: conference-paper
Source: Symposium on VLSI Technology
Authors: C.H. Diaz, K.L. Young, J.H. Hsu, J.C.H. Lin, C.S. Hou, C.T. Lin, J.J. Liaw, C.C. Wu, C.W. Su, C.H. Wang, J.K. Ting, S.S. Yang, K.Y. Lee, S.Y. Wu, C.C. Tsai, H.J. Tao, S.M. Jang, S.L. Shue, H.C. Hsieh, Y.Y. Wang, C.C. Chen, S.C. Yang, S. Fu, S.Z. Chang, T.C. Lo, J.Y. Wu, J.S. Shy, C.W. Liu, S.H. Chen, B.L. Lin, B.K. Liew, T. Yen, C.H. Yu, Y.C. Chao, M.S. Liang, C. Wang, J.Y.C. Sun
Institution: Taiwan Semiconductor Manufacturing Company (Taiwan)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W2139692663