Dual-V/sub T/ SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation
Year: 2000
Type: conference-paper
Abstract: Comparisons among different dual-V/sub T/ design choices for a large on-chip cache with single-ended sensing show that the design using a dual-V/sub T/ cell and low-V/sub T/ peripheral circuits is the best, and provides 10% performance gain with 1.2x larger active leakage power, and 1.6% larger cell area compared to the best design using high-V/sub T/ cells.
Authors: F. Hamzaoglu, Y. Ye, A. Keshavarzi, K. Zhang, S. Narendra, S. Borkar, M. Stan, V. De
Institutions: Intel (United States), University of Virginia
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: bronze
OpenAlex ID: W2140348248