Work

A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS

Year: 2011

Type: conference-paper

Source: Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference

DOI: 10.1109/isscc.2011.5746235

Authors: Hyung-Jin Lee, Alexandra M. Kern, Sami Hyvonen, Ian A. Young

Institution: Intel (United States)

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2148769415

FWCI: 2.122

Cites: 4

Cited by: 12

Related to: 10