Work

ACSU Architecture with High Clock Speed for Viterbi Decoder Using T-Algorithm

Year: 2014

Type: article

Authors: Atish A. Peshattiwar, Shashant Jaykar, Tejaswini Panse

Institution: Rashtrasant Tukadoji Maharaj Nagpur University

Language: English

Topic: Error Correcting Code Techniques

Subfield: Computer Networks and Communications

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2174636005

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Related to: 10