Year: 2015
Type: dissertation
Abstract: Classes of problems that exhibit high levels of data reuse have heavy overhead costs due to the necessity of repeated memory accesses.A proposed programmable hardware accelerator using a spatial architecture paired with triggered instructions could solve this class of problems more efficiently.Performance models are useful for evaluating the performance of different applications and design alternatives.This project develops a functional model for this hardware accelerator as well as a simple timing model to allow for examination of the performance of this proposed architecture.Furthermore, convolution, pooling, and non-linearity are implemented as programs on this accelerator in order to show functionality and flexibility present within the system.This project shows the feasibility of a spatial architecture powered by triggered instructions and provides the framework for future testing and prototyping for this problem space.
Author: Matthew W. Fox
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W2288077385