Work

SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing

Year: 2016

Type: article

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

DOI: 10.1109/tcad.2016.2570428

Authors: Yoon Seok Yang, Hrishikesh Deshpande, Gwan Choi, Paul V. Gratz

Institutions: Intel (United States), Texas A&M University

Language: English

Topic: Interconnection Networks and Systems

Subfield: Computer Networks and Communications

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2396539052

FWCI: 0.242

Cites: 42

Cited by: 9

Related to: 10