Area Efficient VLSI Architecture for Square Root Carry Select Adder Using Zero Finding Logic
Year: 2016
Type: conference-paper
Abstract: Binary addition is one of the primitive operations in computer arithmetic. High performance VLSI integer adders are critical elements in general purpose and digital-signal processing processors since they are employed in the design of Arithmetic-Logic Units, in floating-point arithmetic data paths and in address generation units. Speed, delay and area are the performance parameters for any adder. Speed can be achieved by means of Square Root Carry Select Adder (SQRT CSLA). Tradeoff between those parameters plays the major role in designing new architecture. From the structure of SQRT CSLA, there is a scope to reduce area by using Zero Finding Logic (ZFC) technique. By using ZFC technique in SQRT CSLA, 16bit architecture has been developed. The modified architecture has reduced area and power when compared to SQRT CSLA Adder. The adder is implemented on Spartan 3E FPGA and is compared with SQRT CSLA. Result analysis Show that the proposed adder gives reduced memory when compared to SQRT CSLA using ZFC.
Source: Procedia Computer Science
Institution: Jawaharlal Nehru Technological University, Kakinada
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W2515214453