Work

All digital phase locked loop with input clock fail detector

Year: 2015

Type: conference-paper

Source: IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)

DOI: 10.1109/iccic.2015.7435657

Authors: T V Aswathi, P Sathishkumar

Institution: Amrita Vishwa Vidyapeetham

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2532736396

FWCI: 0.832

Cites: 12

Cited by: 3

Related to: 10