Work

Design of delay efficient modified 16 bit Wallace multiplier

Year: 2016

Type: conference-paper

Source: IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology

DOI: 10.1109/rteict.2016.7808163

Authors: G. Challa Ram, D. Sudha Rani, R. Balasaikesava, K. Bala Sindhuri

Institution: SRKR Engineering College

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2575238060

FWCI: 2.325

Cites: 6

Cited by: 33

Related to: 10