Work

Standby and dynamic power minimization using enhanced hybrid power gating structure for deep-submicron CMOS VLSI

Year: 2017

Type: article

Source: Microelectronics Journal

DOI: 10.1016/j.mejo.2017.02.003

Authors: J. Jeba Johannah, Reeba Korah, Maria Kalavathy, Sivanandham

Institutions: St. Joseph’s College of Engineering, Alliance University, Vellore Institute of Technology University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2599764483

FWCI: 0.781

Cites: 25

Cited by: 17

Related to: 10