RAPIDbus architecture and realization
Year: 2018
Type: article
Abstract: RAPIDbus: Architecture and Realization describes a synchronous multiprocessor designed to support sensory processing, image understanding, and control applications. Up to eight board level masters interact with up to eight slaves along a time-multiplexed implementation of a crossbar switch. Two implementations are considered, one based on an Advanced Shottky logic with a bus bandwidth of 16 Mhz and a Versabus host interface. The second implementation, based on an ECL/TTL gate array, permits an estimated 64 Mhz of bus bandwidth and a Versus/Multibus host interface. Segmented memory management a multicast capability between one master and multiple destinations, and a standardized host interface aid in making RAPIDbus an appropriate architecture for robotic applications. (Author)
Source: KiltHub Repository
DOI: 10.1184/r1/6559556
Authors: Willis, John C., Sanderson, Arthur C.
Language: English
Subfield: Computer Networks and Communications
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W267534876