Year: 2009
Type: article
Abstract: Hopfield Neural Network has been used to solve the constraints satisfaction problems.To make these networks solve problem in real time, independent of the size, would require building a massively parallel structure.A CMOS circuit can be used to construct such network to find the solution.Current CMOS technology is reaching its physical limitation in deep submicron regime and new devices are explored which can provide scalability in accordance to Moore's Law.To further increase the network capacity double gate transistors can be used.Double gate MOSFET model of the hysteresis neuron proposed in this thesis utilizes 8 transistors as compared to 60 transistors needed with an operational amplifier's model.This structure not only reduces the count of transistors by 86% but also demonstrates that larger circuits of double gate MOSFETs can be built, bolstering the faith in double gate MOSFET devices as a possible substitute of CMOS devices in a near future.
Author: Amit Parasmal Borundiya
Institution: Ohio University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W2772086202