Work

A 25-Gb/s 270-mW Time-to-Digital Converter-Based $8{\times}$ Oversampling Input-Delayed Data-Receiver in 45-nm SOI CMOS

Year: 2018

Type: article

Source: IEEE Transactions on Circuits and Systems I Regular Papers

DOI: 10.1109/tcsi.2018.2851294

Authors: Sami Ur Rehman, Mohammad Mahdi Khafaji, Corrado Carta, Frank Ellinger

Institution: Technische Universität Dresden

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funder: Bundesministerium für Bildung und Forschung

OpenAlex ID: W2883232255

FWCI: 0.951

Cites: 42

Cited by: 16

Related to: 10