Work

Novel CMOS multi-bit counter for speed-power optimization in multiplier design

Year: 2018

Type: article

Source: AEU - International Journal of Electronics and Communications

DOI: 10.1016/j.aeue.2018.08.015

Authors: Aloke Saha, Rahul Pal, Akhilesh G. Naik, Dipankar Pal

Institutions: Dr. B.C. Roy Engineering College, Birla Institute of Technology and Science, Pilani - Goa Campus

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2888079360

FWCI: 1.433

Cites: 41

Cited by: 41

Related to: 10