Work

Performance Tuning and Analysis for Stencil-Based Applications on POWER8 Processor

Year: 2018

Type: article

Abstract: This article demonstrates an approach for combining general tuning techniques with the POWER8 hardware architecture through optimizing three representative stencil benchmarks. Two typical real-world applications, with kernels similar to those of the winning programs of the Gordon Bell Prize 2016 and 2017, are employed to illustrate algorithm modifications and a combination of hardware-oriented tuning strategies with the application algorithms. This work fills the gap between hardware capability and software performance of the POWER8 processor, and provides useful guidance for optimizing stencil-based scientific applications on POWER systems.

Source: ACM Transactions on Architecture and Code Optimization

DOI: 10.1145/3264422

Authors: Jingheng Xu, Haohuan Fu, Wen Shi, Lin Gan, Yuxuan Li, Wayne Luk, Guangwen Yang

Institutions: Tsinghua University, Imperial College London

Language: English

Topic: Parallel Computing and Optimization Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: bronze

Funders: National Natural Science Foundation of China, China Postdoctoral Science Foundation, Tsinghua University, Engineering and Physical Sciences Research Council

Awards: G1364632020, G1661212419, G2627530790, Application Customisation: Enhancing Design Quality and Developer Productivity, G3110517578, G4045670047, EPSRC Centre for Doctoral Training in High Performance Embedded and Distributed Systems, Event-based parallel computing - partially ordered event-triggered systems (POETS), G5542607319, G6010298044, G6492442049, Exploiting Parallelism through Type Transformations for Hybrid Manycore Systems, G7321677127

OpenAlex ID: W2899342811

FWCI: 2.159

Cites: 41

Cited by: 11

Related to: 10