Work

A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer

Year: 2018

Type: conference-paper

Source: IEEE Asian Solid-State Circuits Conference (A-SSCC)

DOI: 10.1109/asscc.2018.8579267

Authors: Po-Wei Chiu, Muqing Liu, Qianying Tang, Chris H. Kim

Institution: University of Minnesota

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2906869815

FWCI: 0.4

Cites: 10

Cited by: 3

Related to: 10