Work

Development and Verification of Various Formats of Functional Blocks Libraries as a Part of the Design Flow for FPGAs

Year: 2019

Type: conference-paper

Source: IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering

DOI: 10.1109/eiconrus.2019.8657285

Authors: Tatiana V. Garbulina, Vasiliy M. Khvatov, Daniil A. Zheleznikov

Institution: Institute for Design Problems in Microelectronics

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2921106965

FWCI: 1.584

Cites: 3

Cited by: 4

Related to: 10