Work

High-performance InGaAs FinFETs with raised source/drain extensions

Year: 2019

Type: article

Abstract: In this letter we report on high-performance InGaAs FinFETs with optimized on-off trade-off. The InGaAs FinFETs are fabricated on silicon substrate using a CMOS-compatible replacement-metal-gate process. Excellent off-state performance is achieved by introducing source-drain spacers and doped extension regions. Extensions are fabricated using a digital etching process, a cycling etching technique that allows one to carefully control the position of the junction underneath the spacers. FinFETs with gate length of 13 nm show an on-current of 300 μ A μ m −1 at V DD = 0.5 V and fixed I OFF = 100 nA μ m −1 , the highest reported for ultra-scaled Si CMOS-compatible III–V FETs.

Source: Japanese Journal of Applied Physics

DOI: 10.7567/1347-4065/ab2c97

Authors: Clarissa Convertino, Cezar B. Zota, Daniele Caimi, Marilyne Sousa, Kirsten E. Moselund, Lukas Czornomaz

Institution: IBM Research - Zurich

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: bronze

Funder: European Commission

Awards: Revolutionary embedded memory for internet of things devices and energy reduction, Integration of III-V Nanowire Semiconductors for next Generation High Performance CMOS SOC Technologies