Year: 2020
Type: conference-paper
Abstract: The challenge of designing a complex System-on-Chip (SoC) lies in the efficient division of the computation blocks between hardware and software implementation depending on design factors such as computational requirements for multiple complex algorithms, communication between the various sub-modules and frequency of memory access. This paper presents a novel hardware-software co-design and co-verification framework which allows the SoC computation modules to be designed and verified at five abstraction levels. Using High-Level Synthesis (HLS) design methodology, a high level system design is created based on the system specification and requirements. The design model is refined repeatedly from the higher to lower abstraction levels. At each design level, the correctness of the refinement process and the resulting models are verified thoroughly by creating testbenches at the top design level and refining them on each level by using the CoDeCoVe framework. The Fuzzy Vault-based Biometric Encryption System is used as a case study to evaluate the performance of the CoDeCoVe framework. The theoretical analysis and experimental results prove the correctness of the proposed framework.
Source: Procedia Computer Science
Author: Rabia Bakhteri
Institution: University of Toronto
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: diamond
OpenAlex ID: W3033735869