Year: 2012
Type: article
Abstract: This paper constructs fully parallel NN hardware architecture, FPGA has been used to reduce neuron hardware by design the activation function inside the neuron without using lookup table as in most researches, to perform an efficient NN. It consist of two main parts; the first part covers network training using MATLAB program, the second part represents the hardware implementation of the trained network through Xilinx high performance Virtex2 FPGA schematic entry design tools.
Author: Rana D. Abdu-Aljabar
Institution: Nahrain University
Language: English
Subfield: Artificial Intelligence
Field: Computer Science
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $50
OpenAlex ID: W3082995142