Work

8.8 A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver

Year: 2021

Type: conference-paper

Source: Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference

DOI: 10.1109/isscc42613.2021.9365853

Authors: James Bailey, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan

Institution: Huawei Technologies (Canada)

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W3133570290

FWCI: 4.255

Cites: 9

Cited by: 13

Related to: 10