Work

Optimized FPGA Mapping of a Bit-serial Square Root Operator with Minimum Output Delay

Year: 2017

Type: article

Source: International Journal on Information Technology (IREIT)

DOI: 10.15866/ireit.v5i4.14605

Authors: Stéphane Simard, Jean-Gabriel Mailloux, Rachid Beguenane

Institution: Université du Québec à Chicoutimi

Language: English

Topic: Numerical Methods and Algorithms

Subfield: Computational Theory and Mathematics

Field: Computer Science

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W3200535481

FWCI:

Cites:

Cited by: 3

Related to: 10