Work

Hybrid SAR ADC with Improved Energy Consumption and Area

Year: 2021

Type: article

Abstract: This study proposes a capacitor switching scheme that reduces both the energy consumption and area through multiple reference voltages of a capacitive digital to analog converter (CDAC), a component of successive approximation register (SAR) analog to digital converter (ADC). With a 10-bit SAR-ADC, if the reference voltage is used as 3-bit with a 6-bit capacitor array, the energy and area (number of capacitors) are reduced by 99.97 % and 93.75 %, respectively. Furthermore, we propose a switching algorithm that minimizes energy consumption, which is proven analytically.

Source: The Journal of Korean Institute of Electromagnetic Engineering and Science

DOI: 10.5515/kjkiees.2021.32.9.762

Authors: Dong-Hun Lee, Sung-Jun Kim, Gyu-Eon Joe, Hyun-Yeop Lee, Young-Jin Kim

Institutions: Korea Aerospace University, Korea Advanced Institute of Science and Technology

Language: English

Topic: Analog and Mixed-Signal Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: diamond

Funders: Korea Aerospace University, Ministry of Science and ICT, South Korea, Institute for Information and Communications Technology Promotion

Awards: G1639375289, G371439096