Year: 2021
Type: conference-paper
Abstract: In this paper, the influence of temperature and back-gate bias is experimentally investigated on 22 nm FDSOI CMOS process. Cryogenic DC characterization was carried out under various back-gate voltages, Vback, from 2.95 K back to 300 K. An abrupt drop-off in drain current due to intersubband scattering is experienced in the transfer characteristic with a certain Vback. Moreover, resonant and source-to-drain tunneling transports are observed in devices with minimal channel length at cryogenic temperatures. The threshold voltage, VT, and free carrier mobility, µeff, and their dependence on the back-gate voltage over a wide range of temperatures are extracted and discussed in detail. This work aims at investigating the impact of back gate potential on VTand carrier transport at cryogenic temperatures, further paving the way towards up-scaling of quantum computers.
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W3205336513