Work

A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration

Year: 2021

Type: conference-paper

Source: IEEE Asian Solid-State Circuits Conference (A-SSCC)

DOI: 10.1109/a-sscc53895.2021.9634797

Authors: Chih-Sheng Lin, Fu-Cheng Tsai, Jian-Wei Su, Sih-Han Li, Tian-Sheuan Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chih-I Wu, Tuo-Hung Hou

Institutions: National Yang Ming Chiao Tung University, Industrial Technology Research Institute, National Taiwan University

Language: English

Topic: Advanced Memory and Neural Computing

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4200325792

FWCI: 3.869

Cites: 7

Cited by: 11

Related to: 10