Work

An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope

Year: 2023

Type: conference-paper

Source: IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

DOI: 10.23919/vlsitechnologyandcir57934.2023.10185335

Authors: Angxiao Yan, Wei Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Baoyong Chi

Institution: Tsinghua University

Language: English

Topic: Advancements in PLL and VCO Technologies

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

Funder: National Natural Science Foundation of China

OpenAlex ID: W4385192574

FWCI: 4.067

Cites:

Cited by: 9

Related to: 10