Work

Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element

Year: 2024

Type: article

Source: Integration

DOI: 10.1016/j.vlsi.2024.102154

Authors: Sherif M. Sharroush, Yasser S. Abdalla

Institutions: Port Said University, Suez University, Jouf University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4391069646

FWCI: 0.286

Cites: 98

Cited by: 3

Related to: 10