Demonstration of a Stacked CMOS Inverter at 60nm Gate Pitch with Power Via and Direct Backside Device Contacts
Year: 2023
Type: conference-paper
Authors: Marko Radosavljević, C.-Y. Huang, R. Galatage, M. F. Qayyum, J. A. Wiedemer, E. Clinton, D. Bennett, H. Ryu, N. K. Thomas, P. Morrow, T. Michaelos, R. Nahm, N. Briggs, A. Roy, C. C. Kuo, S. Atanasov, S. Ghose, N. Zussblatt, N. Kumar, D. Unluer, M. Beasley, J. M. Tan, L. H. Tan, M. Elkins, S. Cekli, R. Hermann, L. Shoer, M. Abd El Qader, U. Desai, T. Edwards, P. Prasad, J. Armstrong, M. Ghosh, Y.-A. Liao, V. Kapinus, D. Dixit, M. K. Harper, P. Tran, K. L. Cheong, A. Fatehi, A. A. Oni, N. Franco, B. J. Krist, M. V. Metz, G. Dewey, R. Schenker, M. J. Kobrinsky
Institution: Intel (United States)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4391594486