Work

High-Speed Wireline Links—Part II: Optimization and Performance Assessment

Year: 2024

Type: article

Abstract: In Part I of this paper, we described the modeling of a general wireline link architecture. In this part, we provide a scheme for optimizing the link parameters and assessing its performance. The optimization process involves many parameters with constraints coming from application and implementation requirements. A brute-force approach to optimization can take prohibitively long time and may not provide sufficient insight into the design iteration. To address this challenge, we divide the optimization process into specifying fixed parameters, calculating select parameters, and sweeping the rest. We then perform a link performance assessment to determine metrics typically used in wireline systems.

Source: IEEE Open Journal of the Solid-State Circuits Society

DOI: 10.1109/ojsscs.2024.3421868

Authors: Hossein Shakiba, Davide Tonietto, Ali Sheikholeslami

Institutions: Huawei Technologies (Canada), Ottawa Research and Development Centre, University of Toronto

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: gold

Estimated APC paid: $1,995