Year: 2024
Type: conference-paper
Abstract: Resistive random-access memory (ReRAM)-based processing-in-memory (PIM) architecture is an attractive solution for training Graph Neural Networks (GNNs) on edge platforms. However, the immature fabrication process and limited write endurance of ReRAMs make them prone to hardware faults, thereby limiting their widespread adoption for GNN training. Further, the existing fault-tolerant solutions prove inadequate for effectively training GNNs in the presence of faults. In this paper, we propose a fault-aware framework referred to as FARe that mitigates the effect of faults during GNN training. FARe outperforms existing approaches in terms of both accuracy and timing overhead. Experimental results demonstrate that FARe framework can restore GNN test accuracy by 47.6% on faulty ReRAM hardware with a -1 % timing overhead compared to the fault-free counterpart.
Institutions: Washington State University, University of Houston
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: green
Funder: National Science Foundation
Awards: CSR: Small: Processing-in-Memory enabled Manycore Systems to Accelerate Graph Neural Network-based Data Analytics, Collaborative Research: CNS Core: Medium: Exploiting Synergies Between Machine-Learning Algorithms and Hardware Heterogeneity for High-Performance and Reliable Manycore Computing
OpenAlex ID: W4401568697