Work

Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs

Year: 2024

Type: conference-paper

Source: IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

DOI: 10.1109/vlsitechnologyandcir46783.2024.10631386

Authors: Feng-Min Lee, Po-Hao Tseng, Yu-Yu Lin, Yu-Hsuan Lin, Wei-Lun Weng, Nei-Chih Lin, Po-Jung Sung, Chien-Ting Wu, Chih-Chao Yang, Wen-Fa Wu, Chang-Hong Shen, Tuo-Hung Hou, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu

Institutions: Macronix International (Taiwan), Taiwan Semiconductor Manufacturing Company (Taiwan)

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W4401880554

FWCI: 12.03

Cites:

Cited by: 18

Related to: 10