Work

Efficient 1-Bit Hybrid Full Adder Design with Low Power Delay Product Using FinFET-TGDI Technology: Simulation and Comparative Study

Year: 2024

Type: conference-paper

Source: Lecture notes in electrical engineering

DOI: 10.1007/978-981-97-5269-0_21

Authors: Parthiv Bhau, Vijay Savani

Institution: Nirma University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4403552158

FWCI: 0.668

Cites: 31

Cited by: 1

Related to: 10