Work

A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a —62.1-dBc Fractional Spur

Year: 2024

Type: article

Abstract: This article presents a 7-GHz fractional-Ndigital phase-locked loop (DPLL) without any digital pre-distortion (DPD) on the integral nonlinearity (INL) of the digital-to-time converter (DTC) or dither. Utilizing a cascaded fractional divider, the fractional spur offset frequency can be shifted beyond the PLL bandwidth, resulting in less fractional spur degradation at near-integer channels. A pseudo-differential DTC (PD-DTC) technique that can cancel the even-symmetric nonlinearity components is also employed to achieve a better suppression of the fractional spur. Thanks to the aforementioned two techniques, a −62.1-dBc worst-case fractional spur can be achieved without degrading the in-band PLL phase noise (PN) or PLL locking time. Occupying 0.23-mm2area in a 65-nm CMOS process, this PLL can achieve a 143.7-fs integrated jitter with a 100-MHz reference frequency and 8.89-mW power consumption, which translates to a figure-of-merit (FoM) of −247.4 dB.

Source: IEEE Journal of Solid-State Circuits

DOI: 10.1109/jssc.2024.3477498