Work

Design and Optimization of a Synchronous Full Adder with Clock Gating Technique for ALU Design in 22nm Technology

Year: 2024

Type: conference-paper

Source: Asian Conference on Intelligent Technologies (ACOIT)

DOI: 10.1109/acoit62457.2024.10939403

Authors: M P Tejas, Prasenjit Deb

Institution: REVA University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W4409103638

FWCI: 3.341

Cites: 10

Cited by: 5

Related to: 10