Work

High Voltage Design Strategies for Gallium Oxide Power Devices

Year: 2025

Type: article

Abstract: This study employs drift-diffusion simulation to investigate key factors influencing the performance of$\beta $-Ga2O3 FinFETs, demonstrating that enhancement-mode behavior ($V_{\mathrm { th}} \gt 0$) is achievable for$\beta $-Ga2O3 FinFET using a Fin width$W_{FIN}\leq 0.5~\mu $m and doping concentration$N_{d}\leq 1\times 10{^{{16}}}$cm-3. Breakdown voltage and output/transfer characteristics are calculated by using drift-diffusion methodology calibrated by experiments. We found that the metal work function ($\boldsymbol {\varnothing }_{m}$), dielectric constant$(\kappa)$, and unintentional negative interface charge density (-Qf) at the$\beta $-Ga2O3/dielectric interface significantly impact Vth, with a high$\varnothing _{m}$being necessary for enhancement mode (E-mode) operation. To achieve 5kV breakdown, a$W_{FIN}$of 200 nm requires a fin thickness$(T_{FIN})$of$0.8~\mu $m, a$W_{FIN}$of 400 nm requires$T_{FIN} {\gt }$$1.2~\mu $m, and a$W_{FIN}\ {\gt }$600 nm requires$T_{FIN}\ {\gt }$$2~\mu $m. From$W_{FIN}\ $of 200 nm to 400 nm, DIBL (drain induced barrier lowering, i.e., Vth /Vds) increases by 300%, while from 400 to 600 nm, it rises by only 100%. The presence of -Qf enhances the breakdown voltage by mitigating DIBL-related failure mechanisms and by redistributing the electric potential away from the gate dielectric and deeper into the$\beta $-Ga2O3 drift region. A controllable and relatively defect-free process was developed for Ga2O3 metal-insulator-semiconductor (MIS) structures, enabling improved interface quality. Capacitance–voltage measurements and progressive annealing studies demonstrate enhanced device stability and reduced hysteresis for the proposed FinFET application. Finally, an optimized$\beta $-Ga2O3 fin etch process was developed on the KLA SPTS SynapsEtch™ module for Ga2O3 technology integration.

Source: IEEE Transactions on Semiconductor Manufacturing

DOI: 10.1109/tsm.2025.3597872