A Power Transistor Active Gate Driver With Two-Level Miller Plateau Detection and Driving Device Equalization Using 180-nm HV BCD Process
Year: 2025
Type: article
Abstract: The configuration of the active gate driver (AGD) significantly impacts how well power semiconductor devices work and how efficient they are. This research presents a new AGD single chip design that identifies the Miller plateau when the signal is turning on and off by utilizing a two-level Miller detector precisely. Moreover, it includes a power gating mechanism to lower the AGD’s power usage. Furthermore, it comes with an Equalizer to guarantee the best use of all MOS devices in the buffer arrays. It is fabricated using TSMC 180-nm High Voltage Bipolar-CMOS-DMOS (HV BCD) process. By conducting thorough measurements across various conditions, its functionality was confirmed at an operating frequency of 500 kHz. Based on the measurement results, the average total power dissipation with power gating is 787 mW. In addition, its power gating mechanism shows a notable decrease of 10% in static power dissipation.
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: gold
Estimated APC paid: $2,075
OpenAlex ID: W4416714570