Year: 2025
Type: conference-paper
Abstract: Functional verification techniques, particularly assertion-based verification, play a critical role in ensuring both correctness and security of modern hardware designs. In this paper, we propose and integrate a spectrum of formal and assertion-driven methods that extend conventional functional verification to address emerging security threats-ranging from stealthy Hardware Trojans (HTs) to adversarial cyber-attacks and cache side-channel exploits. First, we review traditional formal verification approaches such as SAT, BDD, and SCA, and discuss their adaptation to approximate computing and resource-bounded contexts. Next, we present an assertion-driven HT-detection paradigm at RTL, using control-flow graph matching and LTL-based specification mining with a hybrid similarity metric. We then demonstrate three complementary assertion- based methodologies for uncovering hardware secu-rity vulnerabilities: (1) deriving countermeasure assertions from an extracted finite-state machine model of an HT trigger; (2) automatically mining ISA-aware temporal assertions for RISC- V processors to detect embedded Trojans; and (3) mining temporal assertions from vehicle-dynamics traces to detect adversarial cyber attacks in autonomous vehicles. Finally,wepropose a formal assertion-generation framework for securing RTL designs against cache side-channel attacks and HT insertions-generating security assertions for both cache memory and RISC-V processor implementations, and validating their efficacy against known CSCAs and Trojan benchmarks. Through these case studies, we demonstrate that assertion-based verifi-cation not only enhances functional correctness guarantees but also provides a high-fidelity, scalable mechanism for detecting and locallzing a diverse range of hardware security threats.
Source: Proceedings
Language: English
Subfield: Hardware and Architecture
Field: Computer Science
Domain: Physical Sciences
Open Access status: green
OpenAlex ID: W4416714701